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MOTOROLA
SEMICONDUCTOR TECHNICAL
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MC33690 Standalone Tag Reader Circuit STARC
The Standalone Tag Reader Circuit (STARC) is an integrated circuit dedicated to the automotive immobilizer applications. It combines on the same chip all the circuitry to interface with a transponder : antenna drivers and demodulator. A low dropout voltage regulator and a physical interface fully compatible with the ISO 9141 norm are also available. The Standalone Tag Reader Circuit is fabricated with the SMARTMOSTM3.5 technology. This process is a double layer metal, 1.4m, 45V technology, combining CMOS and bipolar devices.
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STANDALONE TAG READER CIRCUIT
Contactless 125kHz tag reader module : - Self synchronous sample & hold demodulator - Amplitude or phase modulation detection - High sensitivity - Fast "read after write" demodulator settling time - Low resistance and high current antenna drivers : 2 @ 150mA (typ.) - Bidirectionnal data transmission - Multi tag, multi scheme operation. Low dropout voltage regulator : - Wide input supply voltage range : from 5.5V up to 40V - Output current capability up to 150mA DC with an external power transistor - 5V output voltage with a 5% accuracy - Low voltage reset function - Low current consumption in standby mode : 300A (typ.). ISO 9141 transmitter and receiver module : - Input voltage thresholds ratiometric to the supply voltage - Current limitation - Ouput slew rate control - No external protection device required.
DW SUFFIX Plastic Package CASE 751D SO - 20
Pin Connections
1 2 3 4 5 6 7 8 9 10
VSUP SOURCE GATE TD1 VSS VDD TD2 MODE1 MODE2 RD
20 19 18 17 16 15 14 13 12 11
Tx Rx K AM XTAL1 XTAL2 LVR DOUT CEXT AGND
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ORDERING INFORMATION
Operating Junction Package Temperature Range
T J = -40C to 125C SOIC 20
Device
MC33690DW
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 4.8 (c) Motorola, Inc., 2002.
MC33690
BLOCK DIAGRAM
Figure 1 : Standalone Tag Reader Circuit Optional : external N channel MOS required for sourced current > 50mA. A recommended reference is MMFT 3055VL from Motorola.
VBAT C1 GATE SOURCE VDD 10F VSS 8MHz VDD VSUP
Voltage Regulator
LVR
RA
LA
TD1
XTAL1 XTAL2
R1
CA
RD R2
MODE1
Tag Reader
MODE2 DOUT AM VBAT
TD2 CEXT 10nF AGND CEXT
510 Tx Rx
ISO 9141 Interface
K
(c) Motorola, Inc., 2002.
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MAXIMUM RATINGS
Rating Supply voltage Supply voltage without using the voltage regulator (V SUP = V DD ) Voltage on SOURCE Current into/from GATE Voltage on GATE Voltage on pins : MODE1/2, CEXT, DOUT, LVR, XTAL1/2, Rx, Tx Voltage on RD Voltage on K and AM Current on TD1 & TD2 (Drivers on & off) Voltage on AGND ESD voltage capability (HBM, see note 1) ESD voltage capability (MM, see note 1) Solder heat resistance test (10s) Junction temperature Storage temperature
Note 1 : Human Body model, AEC-Q100-002 Rev. C. Machine Model, AEC-Q100-003 Rev. E.
Symbol V SUP V DD
Value V SS -0.3 to +40 V SS -0.3 to +7 V SS-0.3 to +40 0 V SS -0.3 V SS -0.3 to V DD +0.3 10 V SS -3 to 40 300 V SS 0.3 2000 200 260
Unit V V V mA V V V V mA V V V C C C
TJ Ts
170 -65 to +150
THERMAL CHARACTERISTIC
Characteristic Junction to ambiant thermal resistance (SOIC20) Symbol Rth Value 80 Unit C/W
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PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function VSUP SOURCE GATE TD1 VSS VDD TD2 MODE1 MODE2 RD AGND CEXT DOUT LVR XTAL2 XTAL1 AM K Rx Tx Power supply External N channel transistor source External N channel transistor gate Antenna driver 1 output Power and digital ground Voltage regulator output Antenna driver 2 output Mode selection input 1 Mode selection input 2 Demodulator input Demodulator ground Comparator reference input Demodulator output (5V) Low Voltage Reset input/output Oscillator output Oscillator input Amplitude modulation input ISO 9141 transmitter output and receiver input ISO 9141 receiver monitor output ISO 9141 transmitter input Description
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DESCRIPTION
TAG READER MODULE
The Tag Reader module is dedicated for automotive or industrial applications where information has to be transmitted contactless. The tag reader module is a write/read (challenge/ response) controller for applications which demand high security level. The tag reader module is connected to a serial tuned LC circuit which generates a magnetic field power supplying the tag. The use of a synchronous sample & hold technique allows communication with all avalaible tags using admittance switching producing absorption of the RF field. Load amplitude or phase shift modulation can be detected at high bit rates up to 8kHz. 125kHz is the typical operational carrier frequency of the tag reader module with a 8MHz clock.
Figure 2 : Tag Reader block diagram
AM Data RA TD1 LA 1/32 counter 125kHz 1/2 4MHz 8MHz Clock 8MHz
Shutdown 125kHz CA TD2 Interface R1 11.25 , 22.5 , 33.75 , 45 , 56.25 , 67.5 , 78.75 , 90 + 0, -11.25, -22.5, -33.75, -45, -56.25, -67.5, -78.75
Self synchronous sample & hold
Setup & Preload LVR
RD S/H R2
(c) Motorola, Inc., 2002.
+ VDD Buffer 500ns + Buffer 100K VDD Comparator + D C Q Data out 500A AGND CEXT CEXT 10nF MOTOROLA SEMICONDUCTORS PRODUCTS 5
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Read function
When answering to the base station, a transponder generates an absorption modulation of the magnetic field. It results in an amplitude/ phase modulation of the current across the antenna. This information is picked up at the antenna tap point between the coil and the capacitor. An external resistive ladder down scales this voltage to a level compatible with the demodulator input voltage range (see parameter VINRD page 16). The demodulator (see figure 2) consists of : - an input stage (emitter follower), - a sample & hold circuit, - a voltage follower, - a low offset voltage comparator. The sampling time is automatically set to take into account a phase shift due to the tolerances of the antenna components (L and C) and of the oscillator. The allowed phase shift measured at the input RD ranges from -45 to +45. Assuming that the phase reference is the falling edge of the driving signal TD1, this leads to a sampling time phase ranging from -78.75 to 90 with discrete steps of 11.25. After reset condition, the sampling time phase is +11.25. The antenna phase shift evaluation is only done : - after each wake-up command (see pages 10 to 12), - or after reset (see page 7). This is necessary to obtain the best demodulator performances. In order to ensure a fast demodulator settling time after wake up, reset or a write sequence, the external capacitor CEXT is preloaded at its working voltage. This preset occurs 256s after switching the antenna drivers on and its duration is 128s. After wake up or reset, the preset has the same duration but begins 518s after clock settling. After power on reset, VSUP must meet the minimum specified value, enabling the nominal operation of VDD, before the start of the preset. Otherwise the preset must be done by the user through a standby/wake-up sequence.
Write function
Whatever the selected configuration (see page 9), the write function is achieved by switching on/off the output drivers TD1/2. Once the drivers have been set in high impedance, the load current flows alternatively
Figure 3 : Current flow when the buffers are switched off
VDD
RA TD1
ILOAD
LA R1 VDD
CA TD2
(c) Motorola, Inc., 2002.
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VOLTAGE REGULATOR
The low dropout voltage regulator provides a regulated 5V supply for the internal circuitry. It can also supply external peripherals or sensors. The input supply voltage ranges from 5.5V to over 40V. This voltage regulator uses a series combination of high voltage LDMOS and low voltage PMOS transistors to provide regulation. An external low ESR capacitor is required for the regulator stability. The maximum average current is limited by the power dissipation capability of the SO 20 package. This limitation can be overcome by connecting an external N channel MOS in parallel with the internal LDMOS. The threshold voltage of this transistor must be lower than the one of the internal LDMOS (1.95V typ.) in order to prevent the current from flowing into the LDMOS. Its breakdown voltage must be higher than the maximum supply voltage. A low voltage reset function monitors the VDD output. An internal 10A pull-up current source allows, when an external capacitor is connected between LVR and GND, to generate delays at power up (5ms typ. with CReset=22nF) . The LVR pin is also the input generating the internal reset signal. Applying a logic low level on this pin resets the circuit : - all the internal flip flops are reset, - the drivers TD1/2 are switched on.
Figure 4 : Voltage regulator block diagram
VBAT C1
VSUP GATE
1MHz oscillator
Charge pump
N channel LDMOS
SOURCE
Voltage reference and biasing VDD generator VDD reset
+ P channel MOS VDD C2 C3 10F 100nF VDD
10A LVR CReset
Comparator
+
(c) Motorola, Inc., 2002.
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ISO 9141 PHYSICAL INTERFACE
This interface module is fully compatible with the ISO 9141 norm describing the diagnosis line. It includes one transmitter (pin K) and 2 receivers (pins K and AM). The input stages consist of high voltage CMOS triggers. The thresholds are ratiometric to VSUP. A ground referenced current source (2.5A typ.) pulls down the input when unconnected. When a negative voltage is applied on the K or AM lines, the input current is internally limited by a 2k resistor (typ.) in series with a diode. A current limitation allows the transmitter to drive any capacitive load and protects against short circuit to the battery voltage. An overtemperature protection shuts the driver down when the junction temperature exceeds 150C (typ). Once shut down by the overtemperature protection, the driver can be switched on again : - if the junction temperature has decreased below the threshold, - and by applying an off/on command, coming either from the demodulator in configurations A and B or directly applied on the input Tx in configuration C (see pin K status in table 1 page 9). The electromagnetic emission is reduced thanks to the voltage slew rate control (5V/s typ.).
Figure 5 : ISO 9141interface
VDD
2k AM data VSUP GND From configuration controller 2.5A GND VDD VSUP 2k Rx From configuration controller Over temperature detector Tag Reader module output K VDD Command
L line AM
2.5A GND GND
VBAT
K line
Tx Current limitation
(c) Motorola, Inc., 2002.
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COMMUNICATION MODES DESCRIPTION
The STARC offers 3 different communication modes. Therefore it can be used as a standalone circuit connected to an Electronic Control Unit (ECU) through a bus line or it can be directly connected to a microcontroller in case of a single board architecture.
Table 1. Communication modes description Configuration Type Bus type Name Configuration pins Mode1 Mode2 Pin status & function description
K output/input : - demodulator output, - amplitude modulation input - shutdown/wake-up AM must be connected to VSUP DOUT forces a low level K output : - demodulator output AM input : - amplitude modulation input, - shutdown/wake-up DOUT forces a low level DOUT output : - demodulator output AM input : - amplitude modulation input MODE2 input : - shutdown/wake-up K output/input (standalone ISO 9141 interface) : - driven by Tx and monitored by Rx K input (standalone ISO 9141 interface) : - monitored by Rx -Tx disabled
1 wire (VBAT) Standalone 2 wires (VBAT)
A
0
0
B
0
1
x Direct connection to a MCU
2 wires (VDD)
C
1 1
0
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STANDALONE CONFIGURATION WITH ONE WIRE BUS
When a low level is applied on pins MODE1 and MODE2, the circuit is in configuration A (standalone single wire bus configuration, see figure 13 page 18). After power on, the circuit is set into read mode. The demodulator output is directly routed to the ISO 9141 interface output K. The circuit can be set into write mode at anytime by violation of all possible patterns on the single wire bus during more than 1ms. Then the K line achieves the amplitude modulation by switching on/off both antenna drivers. After 1ms of inactivity at the end of the challenge phase (bus in idle recessive one state), the circuit is set back into read mode. The circuit can be put into standby mode by forcing the K line at zero during more than 2 ms after entering the write mode. Once the K line is released, the circuit sends an acknowledge pulse before entering into standby mode. In standby mode, the oscillator and most of the internal biasing currents are switched off. Therefore, the functions (tag reader, ISO 9141 driver) are inactive except the voltage regulator and the ISO 9141 receiver on pin K. The driver output TD1 forces a low level and TD2 a high level. A rising edge on K wakes up the circuit. After completion of the wake-up sequence, the circuit is automatically set in read mode. In configuration A, DOUT and Rx outputs always force a low level, Tx is disabled.
Figure 6 : Mode access description in one wire bus configuration
Read to write mode : K line
read mode
T0 t < T 0 '+T 1 '
1
1
1
0
0
0
write mode
Write to read mode : K line
write mode
t T0
read mode
Write to standby mode : K line
write mode
t T1
T2
T2
acknowledge standby mode
Standby mode to read mode : K line
standby mode wake-up sequence read mode
Figure 7 : Configuration A state diagram
T 0 K line low
write reset read
TD1/2 off K line high < T 0 '
T 0 K line high
K line low
write
TD1/2 switching
T 1 K line low
wake up
K
standby
(c) Motorola, Inc., 2002.
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Timing definitions for a 8MHz crystal: - Tref is crystal oscillator period (125 ns typ.) - T0=8064.Tref = 1.008ms typ. - T0'=7932.Tref = 0.992ms typ. - T1=16256.Tref = 2.032ms typ. - T1'=16128.Tref = 2.016ms typ. - T2=4096.Tref, = 512s typ. T0 is the minimum time required to guarantee that the device toggles from read to write (or from write to read). But indeed, the STARC may toggle from read to write (or from write to read) between T0 and T0'. T1 is the minimum time required to guarantee that the device toggles from write to standby. But indeed, the STARC may toggle in standby between T1 and T1'.
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STANDALONE CONFIGURATION WITH TWO WIRES BUS
When a low level is applied on MODE1 and a high level on MODE2, the circuit is in configuration B (standalone 2 wires bus configuration, see figure 14 page 19). The K pin is set as an output sending the demodulated data. The AM pin is set as a VSUP referenced input pin receiving the amplitude modulation and the shutdown/wake-up commands. Forcing high and low levels on AM achieves the amplitude modulation by switching on/off both antenna drivers. Meanwhile, this amplitude modulation can be monitored on the K output. This allows antenna short and open circuit diagnosis. The circuit can be put into standby mode by forcing the AM line at zero during more than 2 ms. The circuit sends an acknowledge pulse before entering into standby mode In standby mode, the oscillator and most of the internal biasing currents are switched off. Therefore, the functions (tag reader, ISO 9141 driver) are inactive except the voltage regulator and the ISO 9141 receiver on pin AM. The driver output TD1 forces a low level and TD2 a high level. A rising edge on AM wakes up the circuit. After completion of the wake-up sequence, the circuit is automatically set in read mode. In configuration B, DOUT and Rx outputs always force a low level, Tx is disabled.
Figure 8 : Modes access description in two wires bus configuration
Read & write sequences : AM line
data read drivers on
drivers off
1
data write modulation
1
1
data write
0
0
0
K line Entering into standby mode : AM line t T1
acknowledge
1
1
1
0
0
0
AM line monitoring
standby mode
K line
T1
T2
T2
Coming out of standby mode : AM line
standby mode wake-up sequence data read
K line
Figure 9 : Configuration B state diagram
reset TD1/2 switching
AM line low
AM line high AM line high TD1/2 off wake up AM line low T1 AM line low AM
standby
(c) Motorola, Inc., 2002.
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DIRECT CONNECTION TO A MICROCONTROLLER CONFIGURATION
When a high level is applied on MODE1, the circuit is in configuration C (direct connection to a microcontroller configuration, see figure 15 page 19). The demodulated data are sent through DOUT. The AM pin is set as a VDD referenced input pin receiving the AM command. Forcing high and low levels on AM achieves the amplitude modulation by switching on/off both antenna drivers. Meanwhile, this amplitude modulation can be monitored on DOUT. This allows antenna short and open circuit diagnosis. The circuit can be put into standby mode by applying a low level on the MODE2 pin. In standby mode, the oscillator and most of the internal biasing currents are switched off. Therefore, the functions (tag reader, ISO 9141 interface) are inactive except the voltage regulator. The driver outputs TD1 and TD2 are frozen in their state (high or low level) before entering into standby mode. DOUT forces a low level. The ISO 9141 interface K is standalone and can be directly controlled by the input pin Tx and monitored by the output Rx. Applying a logic high level on Tx switches the output driver K on (dominant zero state when an external pull-up resistor is connected between K and VBAT). Applying a logic low level turns the driver off (one recessive state). Rx monitors the voltage at the K pin. When the voltage is below the low threshold voltage, Rx forces a logic low level. When the voltage is above the high threshold voltage, Rx forces a logic high level. In standby mode, Tx is disabled and Rx output monitors the voltage at the K pin.
Figure 10 : Configuration C state diagram
reset TD1/2 switching
AM low
AM high AM high TD1/2 off wake up AM low mode2 low mode2 high mode2 low
standby
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ELECTRICAL CHARACTERISTICS
Typical values reflect average measurements at VSUP=12V and TJ=25C.
SUPPLY CURRENT
6V VSUP 16V, VSS = 0V, TJ = -40C to +125C, unless otherwise noted Parameter
Pin VSUP 9.1 Standby mode current I SUP1 300 1.5 500 2.5 A mA
Symbol
Test Conditions & Comments
Min
Typ
Max
Unit Type
9.2 Operating mode current I SUP2 See note 1 1. Circuit in configuration C, no current sunk from VDD, drivers TD1/2 switched off, Tx forced to low.
VOLTAGE REGULATOR
6V VSUP 16V, VSS = 0V, TJ = -40C to +125C, unless otherwise noted Parameter
Pins VSUP & VDD 1.1 1.3 1.5 1.9 Output Voltage (5.5V V SUP 40V) Total Output Current Load Regulation Output Voltage (5.5V V SUP 40V) V VDD1 I VDD1 V LoadReg1 V VDD2 I VDD2 V LoadReg2 Without external MOS transistor I OUT 50mA Without external MOS transistor 1 to 50mA I OUT change With external MOS transistor, see notes 1 and 2 I OUT 150mA With external MOS transistor 1 to 150mA I OUT change 4.75 4.7 5.0 20 5.0 65 5.25 50 60 5.3 150 150 V mA mV V mA mV
Symbol
Test Conditions & Comments
Min
Typ
Max
Unit Type
1.11 Total Output Current 1.6 Load Regulation
1.4 Line Regulation (6V V SUP 16V) V LineReg I OUT = 1mA -15 -1 mV 1. The stability is ensured with a decoupling capacitor between VDD and VSS : COUT 10F with ESR 3. 2. The current capability can be increased up to 150mA by using an external N channel MOS transistor (see figure 1 page 2). The main characteristics for choosing this component are : VT < 1.8V and BVDSS > 40V.
(c) Motorola, Inc., 2002.
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LOW VOLTAGE RESET
6V VSUP 16V, VSS = 0V, TJ = -40C to +125C, unless otherwise noted Parameter
Pin LVR 1.6 1.7 Low Voltage Reset Low Threshold Low Voltage Reset Hysteresis V LVRON V LVRH I LVRUP R LVR V ILLVR V IHLVR See note 1 and figure 11 VLVR = 2.5V VLVR = 2.5V 4.1 50 5 200 0 4.35 100 10 370 4.6 150 15 500 0.3 x V DD V mV A V
Symbol
Test Conditions & Comments
Min
Typ
Max
Unit Type
1.12 Pull-up Current 1.13 Output Resistance in reset condition 1.14 Input Low Voltage 1.15 Input High Voltage
0.7 x V DD V V DD 1. As the voltage regulator and the low voltage reset are using the same internal voltage reference, it is ensured that the low voltage reset will only occur when the voltage regulator is out of regulation.
Figure 11 : Low voltage reset waveform VDD VLVRON + VLVRH VLVRON LVR
OSCILLATOR
6V VSUP 16V, VSS = 0V, TJ = -40C to +125C, unless otherwise noted Characteristic
Pins XTAL1, XTAL2 8.0 8.1 Input Capacitance Voltage gain V XTAL2 / V XTAL1 C XTAL1 A OSC V XTAL1 = 2.5V V XTAL1 = 2.5V
1
Symbol
Test Condition & Comments
Min
Typ
Max
Unit Type
-
5 25
-
pF -
8.3 Clock input level V XTAL1 1.5 V DD See note Vpp 1. This level ensures the circuit operation with a 8MHz clock. It is applied through a capacitive coupling. A 1M resistor connected between XTAL1 and XTAL2 biases the oscillator input.
(c) Motorola, Inc., 2002.
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TAG READER
6V VSUP 16V, VSS = 0V, TJ = -40C to +125C, unless otherwise noted Parameter
DEMODULATOR (pin RD) 2.0 2.2 2.3 Input Voltage Range Input Modulation Frequency Demodulator Sensitivity V INRD F MOD V SENSE1 6.5V V SUP 16V See figure 12 and note 1 6V V SUP < 6.5V See figure 12 and note 1 See figure 12 Configuration C see note 2 for configurations A and B 3 0.5 4 4 5 5 8 15 V kHz mV
Symbol
Test Conditions & Comments
Min
Typ
Max
Unit Type
2.31 Demodulator Sensitivity
V SENSE2
-
7
30
mV
2.4
Demodulation Delay
t Demod
-
7.5
10
s s s
2.5 2.6
After Write Pulse Settling Time Recovery Time after wake-up or reset from clock stable to demodulator valid output
t Settling1 t Settling2 See note 3
-
394 646
400 700
DRIVERS (pins TD1, TD2) 3.5 Output Carrier Frequency to Crystal Frequency Ratio R FTD/
FXTAL
I LOAD = 150mA DC -
64 2.4
250 4
ns
3.0 Turn on/off Delay 3.1 Driver1/2 Low Side Out. Resistance
t on/off R TDL
I LOAD = -150mA DC 2.1 4 3.2 Driver1/2 High Side Out. Resistance R TDH 1. The sensitivity is measured in the following application conditions : IANTENNA = 50mA peak, VRD = 4V peak, CEXT = 10nF, square wave modulation FMOD=FTD1/32. 2. Not including the delay due to the slew rate of the K output. 3. Clock stable condition implies VXTAL1 meets the specification (see page 15).
Figure 12 : Demodulator parameters definition
VRD VSENSE
Demodulator output (K or DOUT)
tDemod
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ISO 9141 INTERFACE
6V VSUP 16V, VSS = 0V, TJ = -40C to +125C, unless otherwise noted Parameter
Receiver (pins K & AM) 4.0 4.1 4.2 4.3 Input Low Voltage Input High Voltage Input Hysteresis Voltage Biasing Current V IL V IH V HY1 IB I BM tdkrx 0V V IN 16V -3 V IN < 0 -3 0.65 x V SUP 0.4 1 -2 0.65 3 -1 2 0.3 x V SUP 40 1.3 5 10 V V V A mA s V/s V/s V/s V mA mA C
Symbol
Test Conditions & Comments
Min
Typ
Max
Unit Type
4.31 Input Current 4.4 K to Rx delay
Driver (pin K) 5.0 5.1 5.2 5.3 5.4 5.5 Output Falling Edge Slew Rate Output Rising Edge Slew Rate Rise Fall Slew Rates Symmetry Output Low Voltage Input Current (driver switched on or off) Current Limitation Threshold SR F SR R SR SYMETRY
3.5 R Pull-up = 510, see note 1 3.5 -1 I LOAD = 25mA -3V V IN 0V 0V V IN 40V -2 35 130
5 5 0 1.1 50 150
6.5 6.5 1 1.4 0 65 170
V OLK I IK IL
5.6 Thermal Shutdown Threshold TH SDWN 1. Calculated from 20% to 80% of the output swing.
DIGITAL I/O
6V VSUP 16V, VSS = 0V, TJ = -40C to +125C, unless otherwise noted Characteristic
INPUT (pins MODE1, MODE2, AM, TX) 6.0 6.1 6.2 Input Low Voltage Input High Voltage Input Hysteresis Voltage V ILD V IHD V HD 0 0.7 x V DD .24 .7 0.3 x V DD V DD 1 V V V
Symbol
Test Condition & Comments
Min
Typ
Max
Unit Type
OUTPUT (pins DOUT,RX) 7.0 7.1 Output Low Voltage Output High Voltage V OL V OH I LOAD = 500uA I LOAD = -500uA C LOAD =10pF, see note 1 0 0.8 x V DD 0.5 4.6 0.2 x V DD V DD 150 V V ns
7.2 Fall/Rise Time t F/R 1. Calculated from 10% to 90% of the output swing.
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MC33690
APPLICATION SCHEMES
Figure 13 : Standalone configuration with one wire bus
VBAT C1 NC GATE NC SOURCE C2 VSS C3 NC VDD VSS TD1 RD TD2 CEXT
10nF
VSUP
LVR XTAL1 XTAL2
1M
10F 100nF
8.2pF
RA
LA CA
8MHz
8.2pF
R1
R2
STARC
MODE1 MODE2 NC DOUT VSUP AM K
CEXT
VBAT
510
AGND Tx NC Rx
If no external MOS transistor is necessary to increase the voltage regulator current capability, the pins GATE and SOURCE must be left unconnected. In this configuration, the outputs Rx and DOUT force a low level. C1 is not required for the STARC functionality and only acts as a reservoir of energy. To preserve the demodulator sensitivity, CEXT and R2 should be connected to AGND, and VSS connected to AGND using a low resistance path.
(c) Motorola, Inc., 2002.
MOTOROLA SEMICONDUCTORS PRODUCTS 18
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MC33690
Figure 14 : Standalone configuration with two wires bus
VBAT C1 NC GATE NC SOURCE C2 VSS C3 VDD VSS TD1 RD TD2 CEXT
10nF
VSUP
LVR
NC
8.2pF
10F 100nF
RA
LA CA
XTAL1 XTAL2
1M 8.2pF
8MHz
R1
R2
STARC
MODE1 MODE2 NC DOUT K AM
VDD VBAT
510
CEXT
AGND Tx NC Rx
If no external MOS transistor is necessary to increase the voltage regulator current capability, the pins GATE and SOURCE must be left unconnected. C1 is not required for the STARC functionality and only acts as a reservoir of energy. To preserve the demodulator sensitivity, CEXT and R2 should be connected to AGND, and VSS connected to AGND using a low resistance path.
(c) Motorola, Inc., 2002.
MOTOROLA SEMICONDUCTORS PRODUCTS 19
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MC33690
Figure 15 : Direct connection to a microcontroller
VBAT C1 NC GATE NC To microcontroller power supply pin C2 VSS C3 SOURCE VDD VSS TD1 RD TD2 CEXT
10nF
VSUP
To microcontroller port/reset pin LVR XTAL1 XTAL2
1M 8.2pF 8.2pF
10uF 100nF
RA
LA CA
8MHz
R1
R2
VDD
STARC
MODE1 MODE2 DOUT AM K To microcontroller port VBAT
510
CEXT
AGND To microcontroller port Tx Rx
If no external MOS transistor is necessary to increase the voltage regulator current capability, the pins GATE and SOURCE must be left unconnected. C1 is not required for the STARC functionality and only acts as a reservoir of energy. To preserve the demodulator sensitivity, CEXT and R2 should be connected to AGND, and VSS connected to AGND using a low resistance path.
(c) Motorola, Inc., 2002.
MOTOROLA SEMICONDUCTORS PRODUCTS 20
revision 4.8, 5 February 2002
MC33690
Notes
(c) Motorola, Inc., 2002.
MOTOROLA SEMICONDUCTORS PRODUCTS 21
revision 4.8, 5 February 2002
MC33690
Notes
(c) Motorola, Inc., 2002.
MOTOROLA SEMICONDUCTORS PRODUCTS 22
revision 4.8, 5 February 2002
MC33690
Notes
(c) Motorola, Inc., 2002.
MOTOROLA SEMICONDUCTORS PRODUCTS 23
revision 4.8, 5 February 2002
MC33690
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